1. Field of the Invention
The embodiments of the invention generally relate to semiconductor device fabrication, and, more particularly, to the formation of inductive elements on integrated circuit structures using damascene processing.
2. Description of the Related Art
High performance (high-Q value) inductors are integral parts of radio frequency (RF)/wireless circuitry. Fabrication of such high-Q value inductors on an integrated circuit chip can result in significant cost savings and performance improvement. Conventionally, a generally thick (approximately 3 μm) copper (Cu) wiring level is added on top of the existing complementary metal oxide semiconductor (CMOS) back-end-of-the-line (BEOL) processing when a high performance inductor is needed.
However, the disadvantages of this additional wiring level are: (1) a thick Cu wire generally has a large pitch which can adversely impact wiring capability; (2) a thick Cu wire is generally less compatible with the CMOS logic library due to having a much lower resistance; and (3) a thick Cu wiring level generally increases overall fabrication costs significantly. Accordingly, there remains a need for a novel fabrication technique for forming high performance inductors on integrated circuit structures.